The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures for a nanosheet field-effect transistor and methods for forming a structure for a nanosheet field-effect transistor.
Device structures for a field-effect transistor generally include a body region, a source and a drain defined in the body region, and a gate electrode configured to switch carrier flow in a channel formed in the body region. When a control voltage exceeding a designated threshold voltage is applied to the gate electrode, carrier flow occurs in an inversion or depletion layer in the channel between the source and drain to produce a device output current. The body region and channel of a planar field-effect transistor are located beneath the top surface of a substrate on which the gate electrode is supported.
A fin-type field-effect transistor (FinFET) is a non-planar device structure that may be more densely packed in an integrated circuit than planar field-effect transistors. A FinFET may include a fin consisting of a solid unitary body of semiconductor material, heavily-doped source/drain regions formed in sections of the body, and a gate electrode that wraps about a channel located in the fin body between the source/drain regions. The arrangement between the gate structure and fin body improves control over the channel and reduces the leakage current when the FinFET is in its ‘Off’ state in comparison with planar transistors. This, in turn, enables the use of lower threshold voltages than in planar transistors, and results in improved performance and reduced power consumption.
Stacked nanowire or nanosheet field-effect transistors have been developed as an advanced type of FinFET that may permit additional increases in packing density. The body of a stacked nanosheet field-effect transistor may include multiple semiconductor nanosheets arranged in a three-dimensional array with a gate stack formed on the nanosheet channel regions. The gate stack may surround all sides of the channel region of each semiconductor nanosheet in a gate-all-around arrangement.